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RISC-V CPU IP Solution
Nuclei Core Gen
FREQ(MHZ)
TECH
GEN_METHOD
Default
Area Optimized
Performance Optimized
Core Type
N300
NS300
Dual Issue
Dual Issue
PMP
PMP
PMP Entry Number :
8
16
TEE
TEE
Multiply
1-cyc Multiply
2-cyc Myltiply
Divider
33-cyc Divider
17-cyc Divider
B-Extension
B-Extension
F/D-Extension
Not Supported
Single FPU
Double FPU
DSP
DSP
ILM
ILM
Interface :
SRAM
AHBL
ILM Addr Width :
DLM
DLM
Interface :
SRAM
AHBL
DLM Addr Width :
External Access ILM/DLM
External Access ILM/DLM
ICache
ICache
2K
4K
8K
16K
32K
64K
ICACHE Dedicated Bus
ICACHE Data Ram shared with ILM
DCache
DCache
2K
4K
8K
16K
32K
64K
Device Region
Device Region
Non-Cacheable Region
Non-Cacheable Region
ECC
ECC
Private Peripheral Bus
Private Peripheral Bus
Fast Peripheral Bus
Fast Peripheral Bus
Interrupt Number
Nice (Nuclei Instruction Custom Extension)
Nice (Nuclei Instruction Custom Extension)
LOCKSTEP
LOCKSTEP
Security Feature
MPU
BBOX
Stack Checker
Bus Data Polarity
查看大图
