DMA
Core Features
The Nuclei uDMA (Micro Direct Memory Access) controller serves as a hardware approach for direct data transfers between peripherals/memory and memory without CPU intervention, targeting to off-load CPU from transferring big data chunks where required.
  • Support up to 8 mem2mem channels with software configurable priority.
  • Support up to 32 peripheral channels for pa-mem transfers.
  • Support up to 16 (peripheral closely coupled) PER-type of memory-peripheral transfers
  • Support memory access with 1-16 beat(s) incrementing burst type.
  • Support configurable data width 8, 16, 32, 64 bits for memory access(depending on data bus width)
  • Support fixed or increasing address generation algorithm
  • Support m2m continuous or repeat configurable-N times transfer mode
  • Support independent source and destination base address setting, byte, half-word or word aligned
  • Support arbitrary transfer block size within (1M-1) bytes.
  • Support interrupt generation, masking and clearing
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