The Nuclei GMC (General Memory Controller) includes two memory controllers:
• The NOR/PSRAM memory controller
• The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
Interface with static-memory mapped devices including:
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
Burst mode support for faster access to synchronous devices such as NOR Flash memory, PSRAM and SDRAM)
Programmable continuous clock output for asynchronous and synchronous accesses
8-,16- or 32-bit wide data bus
Independent Chip Select control for each memory bank
