HASH_Nuclei SoC IP

HASH

Core Features

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512), the MD5 (message-digest algorithm 5) and SM3 hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications. HMAC is suitable for applications requiring message authentication.
The hash processor computes FIPS (Federal Information Processing Standards) or SM3 approved digests of length of 160,224, 256, 384, 512 bits. It also computes 128 bits digests for the MD5 algorithm.

Suitable for data authentication applications, compliant with:

Support Federal Information Processing Standards Publication FIPS PUB 180-4, Secure Hash Standard (SHA-1 and SHA-2 family),
Support Internet Engineering Task Force (IETF) Request For Comments RFC 1321 MD5 Message-Digest Algorithm,
Support Internet Engineering Task Force (IETF) Request For Comments RFC 2104 HMAC: Keyed-Hashing for Message Authentication, and Federal Information Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message Authentication Code (HMAC),
Support Digital signature and verification of state secrets SM3 standard.
Support Digital signature and verification of state secrets Whirlpool standard.

Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the digest of the whole message.
Automatic 32-bit words swapping to comply with the internal little-endian representation of the input bit-string.
Word swapping supported: bits, bytes, half-words of 32-bit word.
Automatic padding to complete the input bit string to fit digest minimum block size of 512 bits (16 x 32 bits) or 1024 bits (32 x 32 bits).
Fast computation of SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SM3, Whirlpool and MD5:

59 (respectively 51) clock cycles for processing one 512-bit block of data using SHA-1 (respectively SHA-224 SHA-256 or SM3) algorithm
80 clock cycles for processing one 512-bit block of data using Whirlpool algorithm,
51 clock cycles for processing one 512-bit block of data using MD5 algorithm,
75 clock cycles for processing one 1024-bit block of data using SHA-384 or SHA-512 algorithm.

Slave peripheral, accessible through 32-bit word accesses only.
16 x 32-bit words (H0 to H15) for output message digest.
Automatic data flow control with support of direct memory access (DMA) using one channel, 4 words burst transfers are supported.
Interruptible message digest computation, on a block(512 bits or 1024 bits) basis:

Re-loadable digest registers,
Hashing computation suspend/resume mechanism, including using DMA.

One internal input FIFO:

The width of FIFO is 32bits,
The depth of FIFO is 32.

RISC-V Foundation

SICA

China RISC-V Industry Alliance

China RISC-V Alliance

SZICC

HBSIA

CBSIA

SOPIC

武汉光电工业技术研究院

Amlogic

VeriSilicon

LAUTERBACH

TencentOS Tiny

OpenHarmony

PlatformIO

SEGGER

MUCSE

ORITEK

Brite

Innochip Technology

格见构知

AistarTek

exide

HighTec

CALTERAH

BinarySemi

X-EPIC

SILERGY

MachineWare

SIMANGO

TrustKernel

XIAOMI

JINGWEI HIRAIN

SIEMENS EDA

Motorcomm

CHIPWAYS

SWID

taolink-tech

GeoforceChip

ChipIntelli

Witmem

Fisilink

TIH Microelectronics

XinSheng Tech

GigaDevice

ASR

AnLogic

TusStar

Mocro & Nano Institute

RT-Thread

OPEN AI LAB

IAR

HUST

SJTU

WHU

HBUT

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