I2C
Core Features
I2C (Inter-Integrated Circuit) bus Interface serves as an interface between the microcontroller and the serial I2C bus. It provides multimaster capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports the standard mode (Sm, up to 100 kHz), Fast mode (Fm, up to 400 kHz), Fast mode plus mode (Fm+, up to 1MHz) and High-speed mode (Hs-mode, up to 3.4MHz).
Depending on specific device implementation DMA capability can be available for reduced CPU overload.
  • Parallel-bus/I2C protocol converter.
  • Master and Slave capability: the same interface can act as Master or Slave.
  • Two internal FIFOs for transmit and receive data:
    • The width of FIFOs is <8> bit,
    • The depth of FIFOs is <2>.
  • I2C Master features:
    • Clock generation,
    • Start and Stop generation.
  • I2C Slave features:
    • Programmable I2C address detection,
    • Stop bit detection.
  • Generation and detection of 7-bit/10-bit addressing.
  • Support general call software reset.
  • Support different communication speed:
    • Standard Speed (up to 100 kHz),
    • Fast Speed (up to 400 kHz),
    • Fast Speed Plus (up to 1 MHz).
    • High Speed (up to 3.4 MHz).
  • Status flags:
    • Transmitter/Receiver mode flag,
    • End-of-Byte transmission flag,
    • I2C busy flag.
  • Clock Stretching Capability:
    • TX data is not ready,
    • RX data is not be fetched by CPU or DMA-core.
  • Support DMA access with DMA controller for high speed data communication.
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